Exemplary embodiments relate to a multi-chip package and, more particularly, to a multi-chip package including a chip address circuit, in which addresses can be assigned to a plurality of multi-chips using a lead to which an external power supply voltage is supplied.
With the development of the semiconductor industry and user needs, the size and weight of electronic devices have been reduced. Techniques such as a multi-chip package technique are used to achieve size and weight reduction. The multi-chip package technique is a technique in which a plurality of semiconductor chips is packaged as a single package. A multi-chip package employing the technique is advantageous in terms of a reduction in size and weight and of the mounting area, as compared with several packages each including a semiconductor chip.
In the package on which a plurality of chips is mounted as described above, different chip addresses are assigned to the respective chips and a chip selected by an external address is operated. For example, in a package including four chips, an address ‘00’ may be assigned to the first chip, an address ‘01’ may be assigned to the second chip, an address ‘10’ may be assigned to the third chip, and an address ‘11’ may be assigned to the fourth chip. Each of the first to fourth chips is selected according to an input address.
As a method of assigning an address to each chip, there is a method of assigning an address to a pad corresponding to address information by supplying a power supply voltage VDD and a ground voltage VSS upon packaging.
FIG. 1 shows the configuration of a conventional multi-chip package.
Referring to FIG. 1, the multi-chip package includes a first package chip 10 and a second package chip 20. The first package chip 10 includes leads 11A and 11B respectively coupled to an external power supply voltage VDD and a ground voltage VSS, a pad circuit 12 coupled to the leads 11A and 11B through a wire, and an internal circuit 13 coupled to the pad circuit 12 and configured to receive chip address information from the pad circuit 12. The second package chip 20 has the same configuration as the first package chip 10 except the pad of a pad circuit 22 coupled to leads 21A and 21B through a wire. In other words, the first package chip 10 includes a first pad PAD_0 12A wire-bonded to the lead 11A and supplied with the power supply voltage VDD, whereas the second package chip 20 includes a second pad PAD_1 22B wire-bonded to the lead 21B and supplied with the ground voltage VSS. Therefore, they can have different pieces of chip address information.
In the conventional multi-chip package, each chip is to include first and second pads to which the power supply voltage VDD and the ground voltage VSS are respectively supplied in order to assign chip address information to the chip, and each chip is also to include the pads at a limited area. Furthermore, since the leads for supplying the power supply voltage VDD and the ground voltage VSS are closely disposed, there are limitations in coupling the leads with the pads, and addresses may not be assigned to a large number of multi-chips. Accordingly, the limited number of chips may be implemented in a multi-chip package.